This invention relates to the field of bus bridging systems and more particularly to a method and apparatus for bridging one or multiple digital signal processors with a peripheral component interconnect bus.
The use of a Peripheral Component Interconnect (PCI) bus in the embedded systems market is increasing at a rapid pace. PCI originated in the personal computer (PC) industry where it was developed to relieve the input/output (I/O) bottleneck in graphics-oriented personal computer interfaces. However, despite its origins in the PC market, PCI is expanding into industrial and embedded systems applications and has emerged as the de facto local bus standard. This is primarily due to the motivation of designers of high performance embedded systems to leverage component volumes from the PC industry to lower the cost of their products. Large segments of the embedded systems market are rapidly standardizing on PCI, but are facing technical challenges in adapting their processing platforms to PCI architecture.
The ability of digital signal processors (DSPs) to perform high-speed arithmetic, input/output (I/O) and interrupt processing operations has made them popular in communications applications. Currently, DSPs are used in a broad range of embedded consumer and industrial communications products (e.g. cellular phones, modems, call processing systems, wireless base stations, video conferencing systems, routers, etc.). Multiprocessor configurations are also widespread, particularly in communications servers that must support diverse functions and a large number of channels.
The current challenge is to bridge these two merging technologies and provide full function PCI interface solutions for DSPs. In general, a DSP includes a host port interface (HPI) and an external memory interface (EMIF). The HPI is generally a 16 bit slave and the EMIF is generally a 32 bit master (e.g. for the Texas Instruments C6201(trademark) DSP). Traditional solutions involve interfacing directly with the HPI of the DSP. Further, traditional bridging solutions do not provide support for multiple DSPs interfacing with a PCI bus.
object of the present invention is to provide a system for bridging a digital signal processor to a PCI bus.
Another object of the present invention is to provide a system for bridging multiple digital signal processors to a PCI bus.
In accordance with one aspect of the present invention there is provided an apparatus for bridging communications between a first communication endpoint equipped with a two port digital signal processor (DSP) circuit having a DSP master port and a DSP slave port and a second communication endpoint equipped with a peripheral component interconnect (PCI) bus module having a PCI master port and a PCI memory connected to a PCI bus. The apparatus being comprised of an intermediate bus operably connected to the DSP master port and the DSP slave port and a regulating means connecting the PCI bus module to the intermediate bus for regulating access to the intermediate bus and data transfer between the first and second communication endpoints.
In accordance with another aspect of the present invention there is provided a method of carrying out a read transaction over a communications bridge between one communication endpoint equipped with a digital signal processor (DSP) circuit having a DSP master port and a DSP slave port and another communication endpoint equipped with a peripheral component Interconnect (PCI) module having a PCI master port and a PCI slave port, an Intermediate bus being operably connected to the DSP master port, the DSP slave port, the PCI master port, and the PCI slave port. The read method consists of regulating access to the intermediate bus for data transfer between a requesting master port and a requested slave port and transacting date for reading by the requesting master port from the requested slave port.
In accordance with another aspect of the present invention there is provided a method of carrying out a write transaction over a communications bridge between one communication endpoint equipped with a digital signal processor (DSP) circuit having a DSP master port and a DSP slave port and another communication endpoint equipped with a peripheral component interconnect (PCI) module having a PCI master port and a PCI slave port, an intermediate bus being operably connected to the DSP master port, the DSP slave port, the PCI master port, and the PCI slave port. The write method consists of regulating access to the intermediate bus for data transfer between a requesting master port and a requested slave port and transacting date for reading by the requesting master port from the requested slave port.